/*
 * Copyright (C) 2018 Hisilicon Limited.
 *
 * this program is for hisi chip mini ap dma
 *
 * This program is free software; you can redistribute it and /or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version
 */

#ifndef _DMA_DRV_H_
#define _DMA_DRV_H_


#define HISI_IEP_DMA_DEVICE_ID 0xd101

#define DEVDRV_DMA_MSI_MAX_VECTORS 32

#define DEVDRV_DMA_CHAN_NUM 16
#define DMA_CHAN_LOCAL_USED_NUM 6
#define DMA_CHAN_LOCAL_USED_START_INDEX 0
#define DMA_CHAN_REMOTE_USED_NUM 6
#define DMA_CHAN_REMOTE_USED_START_INDEX 6
#define DMA_CHAN_TS_USED_NUM 4
#define DMA_CHAN_TS_USED_START_INDEX 12
#define DMA_DONE_IRQ_NUM 16
#define DMA_DONE_IRQ_BASE 16
#define DMA_ERR_IRQ_NUM 16
#define DMA_ERR_IRQ_BASE 0

#define DMA_ERR_MASK 0x7ffe


#define DEVDRV_DMA_CHANNEL_IDLE_STATE 0x0
#define DEVDRV_DMA_CHANNEL_RUN_STATE 0x1
#define DEVDRV_DMA_CHANNEL_CPL_STATE 0x2
#define DEVDRV_DMA_CHANNEL_PAUSE_STATE 0x3
#define DEVDRV_DMA_CHANNEL_HALT_STATE 0x4
#define DEVDRV_DMA_CHANNEL_ABORT_STATE 0x5


#define DEVDRV_DMA_CQ_HEAD(cq_depth) ((cq_depth)-1)

struct devdrv_dma_sq_node {
    u32 opcode : 4;
    u32 drop : 1;
    u32 nw : 1;
    u32 reserved1 : 2;
    u32 ldie : 1;
    u32 rdie : 1;
    u32 reserved2 : 2;
    u32 attr : 3;
    u32 reserved3 : 1;
    u32 addrt : 2;
    u32 reserved4 : 2;
    u32 pf : 3;
    u32 vfen : 1;
    u32 vf : 8;
    u32 pasid : 20;
    u32 er : 1;
    u32 pmr : 1;
    u32 prfen : 1;
    u32 reserved5 : 1;
    u32 msi : 8;
    u32 flow_id : 8;
    u32 reserved6 : 8;
    u32 th : 1;
    u32 ph : 2;
    u32 reserved7 : 13;
    u32 length;
    u32 src_addr_l;
    u32 src_addr_h;
    u32 dst_addr_l;
    u32 dst_addr_h;
};

struct devdrv_dma_cq_node {
    u32 reserved1;
    u32 reserved2;
    u32 sqhd : 16;
    u32 reserved3 : 16;
    u32 reserved4 : 16;
    u32 vld : 1;
    u32 status : 15;
};

#include "dma_comm_drv.h"

#endif
